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| motorola semiconductor technical data MC14489B m u iti-character led display/lamp driver cmos p svffix plasticoip case73$ pw suff,~ soopackage " case 7510 .. ordering infqrmatjon MC14489Bp plasticdtp MC14489Bdw soop~gec the mc144898 is a flexible light-emitting-diode driver which directly in- terfaces to individual lamps, 7-segment displays, or various combinations of both. leos wired with common cathodes are driven in a multiplexed-by-5 fashion. communication with an mcuimpu is established through a synchro- nous serial port. the mc 144898 features data retention plus decode and scan circuitry, thus relieving processor overhead. a single, current-setting resistor is the only ancillary component required. a single device can drive anyone of the following: a 5-digit display plus decimals, a 4-112-digit display plus decimals and sign, or 25 lamps. a special technique allows driving 5 112 digits; see figure 16. a configuration register allows the drive capability to be partitioned off to suit many additional applica- tions. the on-chip decoder outputs 7-segment-format numerals o to 9, hexa- decimal characters a to f, plus 151etters and symbols. the mc144898 is compatible with the motorola spi and national mi- cro-wiretm serial data ports. the chip's patented 8itgrabbertm registers augment the serial interface by allowing random access without steering or address bits. a 24-bit transfer updates the display register. changing the con- figuration register requires an 8-bit transfer. .operating voltage range of drive circuitry: 4.5 to 5.5 v .operating junction temperature range: -40 to 130c .current sources controlled by single resistor provide anode drive .low-resistance fet switches provide direct common cathode interface .low-power mode (extinguishes the leds) and brightness controlled via serial port .special circuitry minimizes emi when display is driven and eliminates emi in low-power mode .power-on reset (por) blanks the display on power-up, independent of supply ramp up time .may be used with double-heterojunction leds for optimum efficiency .chip complexity: 4300 elements (fets, resistors, capacitors, etc.) bitgrabber is a trademark of motorola inc. microwire is a trademark of national semiconductor corp. revo november 2000
mc1448 9 b mo t orola 2 block diagram 1 bitgrabber configur a tion register 8 bits rx d a t a out 8 2 2 0 12 bitgrabber displ a y register 24 bits nibble mux and decoder rom anode drivers (current sources ) bank switches (fe t s) 1 9 4 5 6 7 ab d a t a in c d e f g h 241/2s t age shift register 11 10 7 4 4 4 4 4 4 4 4 4 4 4 4 18 por 9 1 3 1 5 1 6 1 7 5 5 clock enable oscill a t or and control logic bank 1 bank 2 bank 3 bank 4 bank 5 pin 3 = v dd pin 14 = v ss h dim/bright blank a t o g d c maximum r a tings* ( v oltages referenced to v ss ) symbol parameter v alue unit v dd dc supply v oltage 0.5 to + 6.0 v v in dc input v oltage 0.5 to v dd + 0.5 v v out dc output v oltage 0.5 to v dd + 0.5 v i in dc input current e per pin (includes pin 8) 15 ma i out dc output current e pins 1, 2, 4 7, 19, 20 sourcing sinking 40 10 ma pins 9, 13, 15, 16, 17 sinking 320 pin 18 15 i dd , i ss dc supply current, v dd and v ss pins 350 ma t j chip junction t emperature 40 to + 130 c r q ja device thermal resistance, junctiontoambient (see thermal considerations section) plasti c dip sog package 90 100 c/w t stg storage t emperature 65 to + 150 c t l lead t emperature, 1 mm from case for 10 seconds 260 c * maximu m ratings are those values beyond which damage to the device may occu r . functiona l operation should be restricted to the limits in the electrical characteristics table s or pin descriptions section. this device contains protection circuitry to guar d against damage due to high static volt- ages or electric fields. howeve r , precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highimpedanc e circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an ap- propriat e logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. mc14489 b mo t orola 3 electrical characteristics ( v oltage s referenced to v ss , t j = 40 to 130 c* unless otherwise indicated) symbol parameter t est condition v dd v guaranteed limit unit v dd power supply v oltage range of led drive circuitry e 4.5 to 5. 5 v v dd (stby) minimum standby v oltage bits retained in display and configuration registers, data port fully functional e 3.0 v v il maximum lowlevel input v oltage (data in, clock, enable ) 3.0 5. 5 0.9 1. 65 v v ih minimum highlevel input v oltage (data in, clock, enable ) 3.0 5. 5 2.1 3. 85 v v hys minimum hysteresis v oltage (data in, clock, enable ) 3.0 5. 5 0.2 0.4 v v ol maximum lowlevel output v oltage (data out) i out = 20 m a 3.0 5. 5 0.1 0.1 v i out = 1.3 ma 4.5 0.4 v oh minimum highlevel output v oltage (data out) i out = 20 m a 3.0 5. 5 2.9 5. 4 v i out = 800 m a 4.5 4.1 i in maximum input leakage current (dat a i n cloc k enable ) v in = v dd or v ss 5. 5 2.0 m a (data in, clock, enable) v in = v dd or v ss , t j = 25 c only 5. 5 0.1 i ol minimum sinking current (a, b, c, d, e, f, g, h) v out = 1.0 v 4.5 0.2 ma i oh peak sourcing current e see figure 7 for currents up to 35 ma (a, b, c, d, e, f, g, h) rx = 2.0 k w , v out = 3.0 v , dimmer bit = high 5.0 13 to 17.5 ma rx = 2.0 k w , v out = 3.0 v , dimmer bit = low 5.0 6 to 9 i oz maximum output leakage current (ban k 1 ban k 2 ban k 3 ban k 4 ban k 5) v out = v dd (fet leakage) 5. 5 50 m a (bank 1, bank 2, bank 3, bank 4, bank 5) v out = v dd (fet leakage), t j = 25 c only 5. 5 1 v out = v ss (protection diode leakage) 5. 5 1 r on maximum on resistance (bank 1, bank 2, bank 3, bank 4, bank 5) i out = 0 to 200 ma 5.0 10 w i dd , i ss maximum quiescent supply current device in lowpower mode, v in = v ss or v dd , rx in place, outputs open 5. 5 100 m a same as above, t j = 25 c 5.5 20 i ss maximum rms operating supply current (the v ss leg does not contain the rx current component. see pin descriptions.) device not in lowpower mode, v in = v ss or v dd , outputs open 5. 5 1.5 ma * see thermal considerations section. mc14489 b mo t orola 4 ac electrical characteristics (t j = 40 to 130 c*, c l = 50 p f , input t r = t f = 10 ns) symbol parameter v dd v guaranteed limit unit f clk serial data clock frequenc y , single device or cascaded devices note: refer to clock t w below (figure 1) 3.0 4.5 5. 5 dc to 3.0 dc to 4.0 dc to 4.0 mhz t plh , t phl maximu m propagatio n dela y , clock to data out (figures 1 and 5) 3.0 4.5 5. 5 140 80 80 ns t tlh , t thl maximum output t ransistion t ime, data out (figures 1 and 5) 3.0 4.5 5. 5 70 50 50 ns f r refresh rate e bank 1 through bank 5 (figures 2 and 6) 3.0 4.5 5. 5 na 700 to 1900 700 to 1900 hz c in maximum input capacitance e data in, clock, enable e 10 pf * see thermal considerations section. timing requirements (t j = 40 to 130 c*, input t r = t f = 10 ns unless otherwise indicated ) symbol parameter v dd v guaranteed limit unit t su , t h minimum setup and hold t imes, data in versus clock (figure 3) 3.0 4.5 5. 5 50 40 40 ns t su , t h , t rec minimum setup, hold, ** and recovery t imes , enable versus clock (figure 4) 3.0 4.5 5. 5 150 100 100 ns t w(l) minimum activelow pulse width, enable (figure 4) 3.0 4.5 5. 5 4.5 3.4 3.4 m s t w(h) minimum inactivehigh pulse width, enable (figure 4) 3.0 4.5 5. 5 300 150 150 ns t w minimum pulse width, clock (figure 1) 3.0 4.5 5. 5 167 125 125 ns t r , t f maximum input rise and fall t imes e data in, clock, enable (figure 1) 3.0 4.5 5. 5 1 1 1 ms * see thermal considerations section. * * for a highspeed 8clock access, t h for enable is determined as follows: v dd = 3 to 4.5 v , f clk > 1.78 mhz: t h = 4350 (7500/f clk ) v dd = 4.5 to 5. 5 v , f clk > 2.34 mhz: t h = 3300 (7500/f clk ) where t h is in ns and f clk is in mhz. notes: 1 . this restriction does not apply for f clk rates less than those listed above. for aslowo f clk rates, use the t h limits in the above table. 2 . this restriction does not apply for an access involving more than 8 clocks. for > 8 clocks, use the t h limits in the above table. mc14489 b mo t orola 5 figure 1 . figure 2. 10% v dd 1/f clk d a t a out clock 90% 50% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r bank output 50% 1/f r v ss figure 3 . figure 4. d ata i n clock 50% v alid 50% t su t h v dd v dd clock enable 50% t su t h first clock last clock t rec 50% v dd v dd t w (h ) t w (l) v ss v ss v ss v ss figure 5 . figure 6. test point device under test c l * * include s all probe and fixture capacitance. test point device under test c l * * include s all probe and fixture capacitance. v dd 56 w mc14489 b mo t orola 6 pin descriptions digi t al inter f ace data in (pin 12) serial data input. the bit stream begins with the msb and is shifted in on the lowtohigh transition of clock. when the device is not cascaded, the bit pattern is either 1 byte (8 bits) long to change the configuration register or 3 bytes (24 bits) long to update the display registe r . for two chips cascaded, the pattern is either 4 or 6 bytes, respectivel y . the display does not change during shifting (until enable makes a low tohig h transition) which allows slow serial data rates, if de- sired. the bit stream needs neither address nor steering bits due to the innovative bitgrabber registers. therefore, all bits in the stream are available to be data for the two registers. ran- dom access of either register is provided. that is, the regis- ters may be accessed in any sequence. data is retained in the registers over a supply range of 3 to 5 .5 v . formats are shown in figures 8 through 14 and summarized in t abl e 2. informatio n on the segment decoder is given in t able 1. data in typically switches near 50% of v dd and has a schmitttriggered input bu f fe r . these feature s combine to maximize noise immunity for use in harsh environments and bu s applications . thi s inpu t ca n b e directl y interface d to cmos devices with outputs guaranteed to switch near rail torail. when interfacing to nmos or ttl devices, either a level shifter (mc14504b, mc74hct04a) or pullup resistor of 1 k w to 10 k w must be used. parameters to be considered when sizing the resistor are the worstcase i ol of the driving device, maximum tolerable power consumption, and maxi- mum data rate. clock (pin 1 1 ) serial data clock input. lowtohigh transitions on clock shift bits available at data in, while hightolow transitions shift bits from data out. the chip ' s 241/2stage shift regis- ter is static, allowing clock rates down to dc in a continuous or intermitten t mode. the clock input does not need to be syn- chronous with the onchip clock oscillator which drive s the multiplexin g circuit. eight clock cycles are required to access the configuration registe r , while 24 are needed for the display register when the MC14489B is not cascaded. see figures 8 and 9. as shown in figure 10, two devices may be cascaded. in this case, 32 clock cycles access the configuration register and 48 access the display registe r , as depicted in figure 10. cascading of 3, 4, 5, and 6 devices is shown in figures 1 1 , 12, 13, and 14, respectivel y . also, reference t able 2. cloc k typicall y switche s nea r 50 % o f v dd a n d h a s a schmitttriggere d input bu f fe r . slow clock rise and fall times are tolerated. see the last paragraph of data in for more in- formation. note t o guarantee proper operation of the poweron rese t (por) circuit, the clock pin must not be floated or toggled during powerup. that is, the cloc k pi n mus t b e stabl e unti l th e v dd pin reaches at least 3 v . if control of the clock pin during powerup is not practical, then the mc14489 b must be reset via bit c0 in the c registe r . t o accomplish this, c0 is re- set lo w , then set high. enable (pin 10) activelow enable input. this pin allows the mc14489 b to be used on a serial bus, sharing data in and clock with other peripherals. when enable is in an inactive high state, data out is forced to a known (low) state, shifting is inhibited, and the port is held in the initialized state. t o transfer data to the device, enable (which initially must be inactive high) is taken lo w , a serial transfer is made via data in and clock, and enable is taken high. the lowtohigh transition on enable transfers data to either the configuration or display registe r , dependin g on the data stream length. every rising edge on enable initiates a blanking interval while data is loaded. thus, continually loading the device with the same data may cause the leds on some banks to appear dimmer than others. note t ransitions o n enable mus t no t b e attempted while clock is high. this puts the device out of synchronization with the microcontrolle r . resyn- chronizatio n occur s whe n enable i s hig h and clock is lo w . this input is also schmitttriggered and switches near 50% of v dd , thereby minimizing the chance of loading erroneous data in the registers. see the last paragraph of data in for more information. data out (pin 18) serial data output. data is transferred out of the shift regis- ter through data out on the hightolow transition of clock. this output is a no connect, unless used in one of the man- ners discussed belo w . when cascading mc14489 b ' s, data out feeds data in of the next device per figures 10, 1 1, 12, 13, and 14. data out could be fed back to an mcu/mpu to perform a wraparound test of serial data. this could be part of a sys- te m check conducted at powerup to test the integrity of the system ' s processo r , pc board traces, solder joints, etc. the pin could be monitored at an inline q.a. test during board manufacturing. finall y , data out facilitates troubleshooting a system. displ a y inter f ace rx (pin 8) external currentsetting resisto r . a resistor tied between this pin and ground (v ss ) determines the peak segment drive current delivered at pins a through h. pin 8 ' s resistor ties into a current mirror with an approximate current gain of 10 when bit d23 = high (brighten). with d23 = lo w , the peak current is reduced about 50%. v alues for rx range from 700 w to infin- it y . when rx = (open circuit), the display is extinguished. for proper current control, resistors having 1% tolerance should be used. see figure 7. caution small rx values may cause the chip to overheat if precautions are not observed. see thermal considerations. mc14489 b mo t orola 7 a through h (pins 1, 2, 4 7, 19, 20) anodedriver current sources. these outputs are close- lymatched current sources which directly tie to the anodes of external discrete leds (lamps) or display segment leds. each output is capable of sourcing up to 35 ma. when used with lamps, outputs a, b, c, and d are used to independentl y control up to 20 lamps. output h is used to con- trol up to 5 lamps dependentl y . (see figure 17.) for lamps, the no decode mode is selected via the configuration regis- te r , forcing e, f, and g inactive (low). when used with segmented displays, outputs a through g drive segments a through g, respectivel y . output h is used to drive the decimals. refer to figure 9. if unused, h must be left open. bank 1 through bank 5 (pins 9, 13, 15, 16, 17) diodebank fet switches. these outputs are lowresis- tance switches to ground (v ss ) capable of handling currents of up to 320 ma each. these pins directly tie to the common cathodes of segmented displays or the cathodes of lamps (wired with cathodes common). the display is refreshed at a nominal 1 khz rate to achieve optimum brightness from the leds. a 20% duty cycle is uti- lized. special design techniques are used onchip to accommo- date the high currents with low emi (electromagnetic interfer- ence) and minimal spiking on the power lines. power supp l y v ss (pin 14) mostnegative supply potential. this pin is usually ground. resistor rx is externally tied to ground (v ss ). therefore, the chip ' s v ss pin does not contain the rx current compo- nent. v dd (pin 13) mostpositive supply potential. t o guarantee data integrity in the registers and to ensure the serial interface is functional, this voltage may range from 3 to 6 volts with respect to v ss . for example, within this volt- age range, the chip could be placed in and out of the low power mode. t o adequately drive the leds, this voltage must be 4.5 to 6 volts with respect to v ss . the v dd pin contains the rx current component plus the chip ' s current drain. in the lowpower mode, the current mir- ror and clock oscillator are turned o f f, thus significantly reduc- ing the v dd current, i dd . figure 7. a through h nominal current per output versus rx 35 30 25 20 15 10 5 400 800 1.2 k 2.0 k 2.4 k 2.8 k 3.2 k 3.6 k 4.0 k 1.6 k i oh, peak drive current (ma) 5 v supp l y bit d23 = high (brighten leds) with d23 = lo w , i oh is cut by ~ 50%. rx, external resis t or ( w ) note : drive current tolerance is approximately 15%. table 1. triple-mode segment decoder function table lamp conditions no decodeg) (invoked via bits c1 to c7) 7-segment display characters bank nibble value special decode (invoked via bits c1 to c7) hex decode (invoked via bits c1 to c5) binary msb lsb hexadecimal d b c a " u i i 2 3 $0 $1 $2 $3 l l l l l h l h l l h h c ,',' ,'i on on on on l./ s g , , 8 9 '-i ,-, 'c, ~ $4 $5 $6 $7 h l l h l h h h l h h h on on on on on on on on $8 $9 $a $b i h l l l h l l h h l h l h l h h on ,- u li on on on on on on on ,- l , c' e f $c $0 $e $f ~ h h h h on on on on on on on on 0 on on on on notes: 1. in the no decode mode, outputs e, f, and g are unused and are all forced inactive (low). output h decoding is unaffected, i.e., unchanged from the other modes. the no decode mode is used for three purposes: a. individually controlling lamps. b. controlling a half digit with sign. c. controlling annunciators. examples: am, pm, uhf, kv, mm hg. 2. can be used as capital s. 3. can be used as capital b. 4. can be used as small g. MC14489B 8 motorola @ ~ @ , u i l " o o , h h h h r l h l h mc14489 b mo t orola 9 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? figure 8. t iming diagrams for noncascaded devices ??? ??? ??? d22 ??? d21 ??? d20 ??? d19 ??? d18 ??? ??? d17 ??? d16 ??? ??? d15 ??? d14 ??? ??? d13 ??? d12 ??? d1 1 ??? d10 ??? d9 ??? ??? d8 ??? d7 ??? ??? d6 ??? d5 ??? ??? d4 ??? d3 ??? d2 ??? d1 ??? ??? ??? d0 ??? ??? ??? ??? d23 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 1 msb lsb l = dim leds, h = brighten leds the lsbs of each bank nibble are d0, d4, d8, d12, and d16. bank 5 note: the lowpower (standby) mode places the device c6 c5 c4 c3 c2 c1 c7 2345678 1 msb enable clock da t a in in a static state, thus eliminating emi and mux switching noise. therefore, during precision analog measurements, the lowpower mode could be invoked by a system' s mcu. also, the lowpower mode blanks the display , and could be used to flash the leds on and of f. c0 l = low power mode (blanks the displa y), forced low (l) by power on reset h = normal mode controls bank 1: controls bank 2: l = hex decode, h = depends on c6 controls bank 3: l = hex decode, h = depends on c6 controls bank 4: l = hex decode, h = depends on c7 controls bank 5: l = hex decode, h = depends on c7 see t able 1 l = no decode, h = special decode (refer t o c1, c2, and c3) l = no decode, h = special decode (refer t o c4 and c5) l l l l h h h h l l h h l l h h l h l h l h l h = all h outputs inactive = activ a te h in bank 1 = activ a te h in bank 2 = activ a te h in bank 3 = activ a te h in bank 4 = activ a te h in bank 5 = activ a te h in both banks 1 and 2 = activ a te h in all banks nibble bank 4 nibble bank 3 nibble bank 2 nibble bank 1 nibble see t able 1 enable clcok da t a in lsb (a) configuration register format (1 byte) (b) display register format (3 bytes) note: l = low v oltage level (logic 0), h = high v oltage level (logic 1) l = hex decode, h = depends on c6 mc14489 b mo t orola 10 applic a tions inform a tion figure 9. noncascaded application example: 5 character common cathode led display with t wo intensities as controlled via serial port #5 #4 #3 #2 #1 8 8 8 8 8 8 d a b c e f g bank 5 bank 4 bank 3 bank 2 bank 1 d a b c e f g h optional cmos mcu/mpu + 5 v rx v dd v ss d a t a out rx d a t a in clock enable + 5 v MC14489B ? h lt) ~o~ zt-z ~ ~ ii) ~o~ z~z <~< 00 to figure 10. bit stream formats for two devices cascaded au. ~ ~o~ ~~ i ~~~ ~- --~ ';!?rn ~ffio sa: i w ~ i ~ id 1- c 2: ii: i o (0) c ~ i:;q- ~ i ~~~ aj (!)u)- --gj ~ i ~~q ("i ~ i ~ id i ~ d z ~ i cn ... w ow .51 w a: c o ; iv ... ~ ci ;0= c 0 (j -- 8. ~ q) - u) .51 q) a: >- m ii u) c u - " ~ i/) c ~ q) " .c q) - -c i/) .- c i/) ~~ >..c "'- 'q. i/) ~ .-q) "c.c q) e >. ~ cb ; .c o ~ ~ 0 ~ 01 i/) c c .- ." "c ~ c -q) c q. .0 q) ~ "c ~ . ~ i/) .g' .~ c > 0 q) u "c q) "c !~ ~ ~ '"" q) c .c q) - q) c .c .- -i/) oi~ c ~ .c u ~ 8 "c ~ ~~ .q i/) j, ~ > - u q) ." >. -.c g-.b -" ~ i/) 0 ~j .qi ." .c ~ q) q) > :5 u .a; "' . c .c .-01 q) .- .c.c --" i/) u ~ jg e - >..c = 01 "' ~ '"" 0 :5 .5 .c .!a 1 ~li ? c z q) uj.c ..s: uj ~ -' < q in 1- gi ~ .~ > i gi i ~ i .! dl c =6 ~ 1,) in ~ (j :: figure 11. bit stream formats for three devices cascaded 1/1 .. q) ... 1/1 .51 q) 11: c .2 ~ .. ~ c) ;;: c o u b in ... 41 "cn '61 41 a: >- la "5. in c :: ..: '* c: q) (\1.0 ~ c: . >-b.c: ~ .2' c.q).c. .~ >. q) "c .0 .~ q). u >.~(\1 -9 b .5 o ... ~ w .-c:-1 ~oaj o"cc( ~. z 2.q)w u) c: c:q) (\iq)~ ~ -(\i --- c:-~ .il) .-~ ~ "1!."c u) c: :j .-(\i .2' &ji . 'e~u) o>-q) u(\1>. q)q..o >. .~ c') ~ "ccn q) (\i .c.- q) -~ .= 01 2. -c:u) c::qc: q) (\i e q)"c- .c.c.~ -:j-.r 0ic:~ c: q) . .c: u :j.c.q) "c~c. u) ~ ~ ~-~ oq)j: ->~ j, "' ~ > (\i - :;: e q) uq)q) (\i .-u) -<{ - c. .c: q) .cj ~ u) .- q).c. .~ .!j q) ~? .c: q) .- oi"cu .-"c (\i .c: q) .5 ~"c ~ uj u~-1 (\i (\i [d .5 u ~ q)q)w .o=q) -c:0) ~ .-3 e ~ c. >-:j~ -hc') ~o-: ...~ u) c: q) q) .-->. .c.0).o u c: .-(\i co .c. "' ~ -~ ~q)2. ~ uj >. 0) -1-9c: ajoe c(.-:::. z~c\i wo~ "i:i.b~ q) - "cc:q) .2 (\i > u ~ .- c:q)u .-.c: (\i ~ ... ~ uj (\iq)-1 u).r:aj q) .2' c( >..c:z .o~w , u q) ~~~ b-s .c.~ ...01.- c::j~ o o .. "c ~ ~ , .0 ~ oiu)o c: .-= .-" .o "c~- (\i-1u) q)aj(\1 -a;c("c .c:zq) -w- (\i c:c:c: q) q) .- .c:.c:e ~~~ uj b z "' ~o~ 2 1- 2 < < 00 00 "' ~o~ z t- z < < 00 00 "' :.:=0:.: z i- z < < 00 00 .c 9 "' .c ~ ... .c ~ "' .c ~ "' "' ~o~ zi-z ~ ~ ~~ 00 ~ i ~~ 0) ~, ~ w "'" "'" ~ u 8 ~ ;1 n * m 0> ~ qo ,.. u ~ lt) :11: m 0> ~ v v .- u ~ m =11= id 0) ~ ~ ~ ,- u ~ ~z ~- 0 ~ <.> ~z <- 1" ~~ ~o w ffi ~ "i u < ~~i '"' i ~~ ~o i~ i ~ ~ uji 8 -' 0 ~z <- n ~~ ~o ::j "' ~o~ zlz <~< cd cd "' ~ ~ zgz < < cd cd ii) ~o~ zi-z ~ ~ "' ~o~ z i- z ~ ~ .c ~ m .c ~ ... .c ~ "' .c ~ ... ('ii =11: m 0) ~ ~ ~ ?- u ~ m '#: m 01 ~ q- q- ~ u ~ id =!i: id 0) co ~ ~ ~ () ~ ~5 ~o ,.. i w :11: -j m ~ 0) z rd w ~ q- ~ c:; 8 ~ 5 .< ~~ "1 8 -' (.) ~z <- a ~!; ~o w -' [0 < z w 8 d < '<~ 0 ~i:; ~o uj -' 00 ~ iii i ~ ~ u ~z <- n ~5 ~o => inll. o~ ~=> l>~ ui q) u '> q) c >< in dl c =6 ~ iii --' iv < u z o iv 1- ci. o i g~- ou. f;~ ~~ i ~ ~ ~ >=~ (.!)cn- ajtl: [!:a[;j f-- 1 ~wc cn:l: olr ~cn (,) i ~ 11. ~ ~~~ iij 115!7j~ ~ i~~~ z au. 1=" ~a- ~~ ' 1 ~ ~ ~ ;;:aj ~a(t; 10 8 wc -11: ! ~ i ~ ~ ~ z ou. -0." '< .. a:a:w ::j~u <.?ci)- --> u.<.?w zwc sa: z ~~'"' ~a:- ::i1:!~ (!)00- --> ll(!)w 8~o figure 14. bit stream formats tor six devices cascaded w a: < (.) 1- z 8 ~ ~ ~ z 8 w ir ~ ~ w ir < u ~ 8 w ~ 1- ~ w a: 5 1- z 8 ~ < u 1- z ~ ui ... q) ~ '51 q) a: c o ;: la ... ~ ci ;;: c o (j e: c w ~ ~.; c ~ as .p!.;. (/) q! c.c as - ;. c >. .- as (/) -w .~~ -0- q! 0 l~ ,.. :. ...c 0 q! c w- in c c 0 ~ cj -c c .- 0 -0 .-c " ~ :. w cj-0 10= . c (/) 8 .~ w q! cn ~-0 ..i -0 gi(ow -,..-0 ~ q! ~ ci~~ gi c ~ a: w >- q!~ ca .c- --c c. cj .- ~ .2 ~ 0 :.:. -0 u ~ >u cj ~ 0 0... 1.; > c -:: ~ u - (1j q! c.>. ~~ .-,.. :2"... cjo :2~ w ,.. > -:: (1j u ... (1j q! .e :5 w .a; .c . -.c "' cj :. .- e.c ~ >.u = as ~.c .2 :e -cj .c :. u 0 .c.c ~ (/) ~.- i ~ i ~ ~id z< wffi w b z 15 mc14489 b mo t orola 16 t able 2. register access for t wo or more cascaded devices c i i * configuratio n register access display register access criteria* t otal number of bytes number of leading adon't careo bytes t otal number of bytes number of leading adon't careo bytes if 3n is a multiple of 4 3n 2 3n + 2 2 if 3n 1 is a multiple of 4 3n 1 1 3n + 1 1 if 3n 2 is a multiple of 4 3n 2 0 3n 0 if 3n 3 is a multiple of 4 3n 2 0 3n 0 * n = number of devices that are cascaded. for example, to drive 10 digits, 2 devices are cascaded; therefore, n = 2. t o drive 35 digits, seven devices are cascaded; therefore n = 7. figure 15. commoncathode led display with dialadjusted brightness v ss cmos mcu/mpu rx led displ a y MC14489B 85 + 5 v r1 r2 v dd + 5 v note : r1 limits the maximum current to avoid damaging the display and/or the mc14489 b due to overheating. see the thermal considerations section. an 1/8 watt resistor may be used for r1. r2 is a 1 k w or 5 k w potentiometer ( 1/8 watt). r2 may be a lightsensitive resisto r . mc14489 b mo t orola 17 figure 16. driving 5 1/2 digits 4 universa l overflow (a1o or ahalfdigito) MC14489B 5 h 3 a t o g 3 2 1 bank outputs 7 use t o drive lamp or minus sign 5digit displ a y input lines note : a universal overflow pins out all anodes and cathodes. mc14489 b mo t orola 18 figure 17. 25lamp application 3 bank 5 bank 4 bank 3 bank 2 bank 1 d a b c e f g h cmos mcu/mpu nc nc nc mc14489 b these lamps dependent l y controlled with bits d20, d21, and d22* these lamps independent l y controlled with bits d0 t o d19 * i f required, this group of lamps can be independently controlled. t o accomplish independent control, only connect lamps to bank 1 and bank 2 for output h (two lamps). then, use bits d20, d21, and d22 for control of these two lamps. mc14489 b mo t orola 19 figure 18. 4digit display plus decimals with four annunciators or 41/2digit display plus sign 4 cmos mcu/mpu a t o d bank 1 to bank 4 bank 5 MC14489B 4 4 e t o h 3 4 ? figure 19. compact display system with three components input lines 3 8 14 mc14489 b muxed 5digit monolithic displ a y (cluster) hewlett p ackard 50827415 or equi v alent 1 2 3 6 2 1 0 8 5 1 1 3 4 9 7 6 5 4 2 1 20 19 17 16 15 13 9 7 mc14489 b mo t orola 20 thermal consider a tions the mc14489 b is designed to operate with a chipjunction temperatur e (t j ) ranging from 40 to 130 c, as indicated in the electrical characteristics tables. the ambient operating temperatur e range (t a ) is dependent on r q ja , the internal chip current, how many anode drivers are used, the number of bank drivers used, the drive current, and how the package is cooled. the maximum ratings table gives the thermal resis- tance, junctiontoambient, of the mc14489 b mounted on a pc board using natural convection to be 90 c per watt for the plastic di p . the sog thermal resistance is 100 c per watt. the following general equation (1) is used to determine the power dissipated by the mc14489 b . p t = p d + p i (1) where p t = t otal power dissipation of the mc14489 b p d = power dissipated in the driver circuitry (mw) p i = power dissipated by the internal chip circuitry (mw) the equations for the two terms of the genera l equation are: p d = (i oh ) (n)(v dd v led )(b/5) (2) (3 ) p i = (1.5 ma)(v dd ) + i rx (v dd i rx rx) where i oh = peak anode driver current (ma) i rx =i oh /10, with i oh = the peak anode driver current (ma) when the dimmer bit is high n = number of anode drivers used b = number of bank drivers used r x = external resistor value (k w ) v dd = maximum supply voltage, referenced to v ss (volts) v led = minimum anticipated voltage drop across the led 1.5 m a = operating supply current of the mc14489 b the following two examples show how to calculate the maximum allowable ambient temperature. w orstcase analysis example 1: 5digit display with decimals (5 banks and 8 anode drivers) dip without heat sink on pc board i oh = 20 ma max v led = 1.8 v min v dd = 5.25 max p d = (20)(8)(5.25 1.8)(5/5) = 552 mw ref. (2) p i = (1.5)(5.25) + 2[5.25 2(2)] = 10 mw ref. (3) therefore, p t = 552 + 10 = 562 mw ref. (1) and d t chip = r q ja p t = (90 c/w)(0.562) = 51 c finall y , the maximum allowable t a = t j max d t chip = 130 51 = 79 c that is, if t a = 79 c, the maximum junction temperature is 130 c. the chip ' s average temperature for this example is lower than 130 c because all segments are usually not illumi- nated simultaneously for an indefinite period. w orstcase analysis example 2: 16 lamps (4 banks and 4 anode drivers) sog without heat sink on pc board i oh = 30 ma max v led = 1.8 v min v dd = 5.5 max p d = (30)(4)(5.5 1.8)(4/5) = 355 mw ref. (2) p i = (1.5)(5.5) + 3[5.5 3(1.0)] = 16 mw ref. (3) therefore, p t = 355 + 16 = 371 mw ref. (1) and d t chip = r q ja p t = (100 c/w)(0.371) = 37 c finall y , the maximum allowable t a = t j max d t chip = 130 37 = 93 c t o extend the allowable ambient temperature range or to reduce t j , which extends chip life, a heat sink such as shown in figure 20 can be used in highcurrent applications. alter- nativel y , heatspreader techniques can be used on the pc board, such as running a wide trace under the MC14489B and using thermal paste. wide, radial traces from the mc14489 b leads also act as heat spreaders. a a vid #5804 or equivalent ( t el. 603/5244443, f a x 603/5281478) motorola cannot recommend one supplier over another and in no way suggests that this is the only heat sink supplie r . figure 20. heat sink t able 3. led lamp and commoncathode display manufacturers supplier qt optoelectronics hewlettpackard (hp), components group industrial electronic engineers (iee), component products di v . purdy electronics corp., and product line note : motorol a cannot recommend one supplier over another and in no way suggests that this is a complete listing of led suppliers. mc14489 b mo t orola 21 p ackag e dimensions p suffix plastic dip case 73803 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0. 1 10 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min mi n max max inches millimeters dim a b c d e f g j k l m n notes: 1 . dimensioning and t olerancing per ansi y14.5m, 1982. 2 . controlling dimension: inch. 3 . dimension l t o center of lead when formed p arallel. 4 . dimension b does not include mold flash. -a- c k n e gf d 20 pl j 20 pl l m - t - se a ting plane 1 1 0 1 1 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b dw suffix sog p ackage case 751d04 notes: 1 . dimensioning and t olerancin g per ansi y14.5m, 1982. 2 . controlling dimension: millimeter. 3 . dimensions a and b do not include mold protrusion. 4 . maximum mold protrusion 0.150 (0.006) per side. 5 . dimension d does not include dambar protrusion. allo w able dambar protrusion shall be 0.13 (0.005 ) t o t al in excess of d dimension a t maximum m a teria l condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t se a ting plane m r x 45 dim min max min max inche s millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 mc14489 a 22 motorol a reserves the right to make changes without further notice to any products herein. motorola makes no warrant y , representatio n o r guarante e regarding th e suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specificall y disclaims any and all liabilit y , including without limitation consequential or incidental damages. a t ypicalo parameters which may be provided in motorola dat a sheets and/or specifications can and do vary in di f ferent applications and actual performance may vary over time. al l operatin g parameters , includin g a t ypicalso mus t be validated for each customer application by custome r ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others . motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the bod y , or other application s intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occu r . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola an d it s o f ficers, employees, subsidiaries, a f filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectl y , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorol a was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/a f firmativ e action employe r . mfax is a trademark of motorola, inc. how to reach us: us a / europ e / locations not listed : motorola literature distribution; ja p an : nippon motorola ltd.; spd, strategic planning o f fice, 141, p .o. box 5405, denve r , colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, t okyo, japan. 81354878488 customer focus center: 18005216274 mfa x ? : rm f ax0@email.sps.mot.co m t ouch t one 1 6022446609 asi a / p acific : motorola semiconductors h.k. ltd.; silicon harbor center, m o t o r o l a f a x b a c k s y s t e m us & canada on l y 18007741848 2 dai king street, t ai po, n. t ., hong kong. fax: 85226666123 http://sps.motorola.com/mfax/ home p age : http://mot-sps.com/ mc14489 b |
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